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HT48F50E i/o flash type mcu with eeprom rev. 1.50 1 july 28, 2009 general description the HT48F50E is an 8-bit high-performance, risc ar - chitecture microcontroller devices specifically designed for multiple i/o control product applications. device flex - ibility is enhanced with their internal special features such as power-down and wake-up functions, oscillator options, buzzer driver, etc. these features combine to ensure applications require a minimum of external com - ponents and therefore reduce overall product costs. having the advantages of low-power consumption, high-performance, i/o flexibility as well as low-cost, these devices have the versatility to suit a wide range of application possibilities such as industrial control, con - sumer products, subsystem controllers, etc. the device utilises a flash type program memory, and therefore have multi-programmable capabilities offering the advantages of easy and efficient program updates. the non-volatile internal eeprom also offers the capa - bility of storing information such as product part num - bers, calibration data and other specific product information. etc. the device is fully supported by the holtek range of fully functional development and pro - gramming tools, providing a means for fast and efficient product development cycles. features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v f sys =12mhz: 4.5v~5.5v multi-programmable flash type program memory: 409615 eeprom data memory:256 8 ram data memory:160 8 max. 33 bidirectional i/o with pull-high options external interrupt input shared with an i/o line an 8-bit programmable timer/event counter with overflow interrupt and 8-stage perscaler a 16-bit programmable timer/event counter with overflow interrupt two timer external inputs crystal and rc system oscillator watchdog timer function pfd/buzzer driver outputs power down and wake-up feature for power saving operation up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 6-level subroutine nesting bit manipulation instructions table read function 63 powerful instructions all instructions executed in 1 or 2 machine cycles low voltage reset function full suite of supported hardware and software tools available flash program memory can be re-programmed up to 100,000 times flash program memory data retention > 10 years eeprom data memory can be re-programmed up to 1,000,000 times eeprom data memory data retention > 10 years isp (in-system programming) interface 28-pin skdip/sop/ssop, 48-pin ssop package technical document tools information faqs application note ha0075e mcu reset and oscillator circuits application note
block diagram pin assignment HT48F50E rev. 1.50 2 july 28, 2009
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pin description pin name i/o configuration option description pa0~pa7 i/o pull-high* wake-up cmos/schmitt trigger input bidirectional 8-bit input/output port. each pin can be configured as a wake-up input by configuration option. software instructions determine if the pin is a cmos output or input. configuration options determine if all pins on this port have pull-high resistors and if the inputs are schmitt trigger or non-schmitt trigger. pb0/bz pb1/bz pb2~pb7 i/o pull-high* i/o or bz/bz bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on this port have pull-high resistors. pins pb0 and pb1 are pin-shared with bz and bz , respectively. pc0~pc7 i/o pull-high* bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on this port have pull-high resistors. pd0~pd7 i/o pull-high* bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on this port have pull-high resistors. pg0/int i/o pull-high* bidirectional 1-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if the pin has a pull-high resistor. pg0 is pin-shared with external interrupt pin int . tmr0 i timer/event counter 0 external schmitt trigger input pin (without pull-high re - sistor). tmr1 i timer/event counter 1 external schmitt trigger input pin (without pull-high re- sistor). osc1 osc2 i o crystal or rc osc1, osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the sys- tem clock at 1/4 frequency. res i schmitt trigger reset input. active low. vdd positive power supply vss negative power supply, ground note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. individual pins cannot be selected to have pull-high resistors. if the pull-high configuration is chosen for a particular port, then all input pins on this port will be connected to pull-high resistors. 3. configuration options determine if the pins on pa are cmos inputs or schmitt trigger inputs. 4. pins pc5~pc7 and pd0~7 only exist on the 48-pin package. on the 28-pin package, these pins are not available. 5. unbounded pins should be setup as outputs or as inputs with pull-high resistors to conserve power. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT48F50E rev. 1.50 3 july 28, 2009
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v f sys =12mhz 4.5 5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz 12ma 5v 35ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz 12ma 5v 2.5 4 ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz 48ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset lvr enabled 2.7 3.0 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (rc osc, crystal osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz 4.5v~5.5v 400 12000 khz f timer timer i/p frequency (tmr) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz 4.5v~5.5v 0 12000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s HT48F50E rev. 1.50 4 july 28, 2009
symbol parameter test conditions min. typ. max. unit v dd conditions t wdt1 watchdog time-out period (wdt internal clock source) 3v without wdt prescaler 11 23 46 ms 5v 8 17 33 ms t wdt2 watchdog time-out period (instruction clock source) without wdt prescaler 1024 *t sys t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 *t sys t lvr low voltage reset time 1 2ms t int interrupt pulse width 1 s note: *t sys =1/f sys eeprom a.c. characteristics ta=25 c symbol parameter v cc =5v10% v cc =2.2v10% unit min. max. min. max. f sk clock frequency 0201mhz t skh sk high time 250 500 ns t skl sk low time 250 500 ns t css cs setup time 50 100 ns t csh cs hold time 0 0 ns t cds cs deselect time 250 250 ns t dis di setup time 100 200 ns t dih di hold time 100 200 ns t pd1 do delay to 1 250 500 ns t pd0 do delay to 0 250 500 ns t sv status valid time 250 250 ns t pr write cycle time 5 5ms HT48F50E rev. 1.50 5 july 28, 2009
HT48F50E rev. 1.50 6 july 28, 2009 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the range of devices take ad - vantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crys - tal/resonator or rc oscillator is subdivided into four in- ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. when the rc oscillator is used, osc2 is freed for use as a t1 phase clock synchronizing pin. this t1 phase clock has a frequency of f sys /4 with a 1:3 high/low duty cycle. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications # 7 8 9 " : 7 8 ! 1 9 # 7 8 ; 1 9 " : 7 8 9 # 7 8 ; + 9 " : 7 8 ; 1 9 ; 1 ; + 8 9 # 1
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system clocking and pipelining # 7 1 " : 7 1 # 7 + # % 1 + 0 / . - " ( < = * > ? 1 + @ a ( ( " ( < ( ? 1 + @ a = = 6 " : 7 + # 7 0 # 7 - " : 7 - # 7 , instruction fetching
HT48F50E rev. 1.50 7 july 28, 2009 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call , that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is se - lected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in- serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 6 levels and is neither part of the data nor part of the program space, and can neither be read from nor written to. the activated level is indexed by the stack pointer, sp, which can also neither be read from nor written to. at a subroutine call or interrupt ac - knowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its pre - vious value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in- struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. mode program counter bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 000000000000 external interrupt 000000000100 timer/event counter 0 overflow 000000001000 timer/event counter 1 overflow 000000001100 skip program counter + 2 loading pcl pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc11~pc8: current program counter bits @7~@0: pcl bits #11~#0: instruction code address bits s11~s0: stack register bits
HT48F50E rev. 1.50 8 july 28, 2009 arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti flash program memory the program memory is the location where the user code or program is stored. for this device the program memory is a flash type, which means it can be pro - grammed and reprogrammed a large number of times, allowing the user the convenience of code modification using the same device. by using the appropriate pro - gramming tools, these devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming. organization the program memory has a capacity of 4k by 15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the external interrupt. if the ex - ternal interrupt pin on the device goes low, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 008h this internal vector is used by the timer/event coun - ter 0. if a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. location 00ch this internal vector is used by the timer/event coun - ter 1. if a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defines the lower 8-bit address of the look-up table.

( b 1 ( b + ( b 0 ( b / ( b . ( b - 1 . 2 1 $ @ 2 2 2 @ 2 2 / @ 2 2 $ @ 2 2 @ 2 1 2 @ @ * " : % * " b 2 % * 2 1 / @ " b 1 % * program memory structure
HT48F50E rev. 1.50 9 july 28, 2009 after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will have uncertain values. the following diagram illustrates the addressing/data flow of the look-up table: table program example the following example shows how the table pointer and table data is defined and retrieved from the HT48F50E device. this example uses raw table data located in the last page which is stored there using the org state - ment. the value at this org statement is 0f00h which refers to the start address of the last page within the 4k program memory of the microcontroller. the ta - ble pointer is setup here to have an initial value of 06h. this will ensure that the first data read from the data ta - ble will be at the program memory address 0f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first ad - dress of the present page if the tabrdc [m] instruc - tion is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] in - struction is executed.

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# 4 c ( ) 4 c look-up table tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 0f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 0f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 : : org 300h ; sets initial address of HT48F50E last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
HT48F50E rev. 1.50 10 july 28, 2009 because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. in circuit programming the provision of flash type program memory gives the user and designer the convenience of easy upgrades and modifications to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit. this provides manufacturers with the possibility of man - ufacturing their circuit boards complete with a pro - grammed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. pin name function pa0 serial data input/output pa4 serial clock res device reset vdd power supply vss ground the program memory and eeprom memory can both be programmed serially in-circuit using a 5-wire inter - face. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two addi - tional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supple - mentary literature. ram data memory the ram data memory is a volatile area of 8-bit wide ram internal memory and is the location where tempo - rary information is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed loca - tions and are necessary for correct operation of the de - vice. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of ram data memory is reserved for gen- eral purpose use. all locations within this area are read and write accessible under program control. organization the ram data memory is subdivided into two banks, known as bank 0 and bank 1, all of which are imple- mented in 8-bit wide ram. most of the ram data mem- ory is located in bank 0 which is also subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the ram data memory for all devices is the address 00h, and the last data memory address is ffh . registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111@7@6@5@4@3@2@1@0 table location note: pc11~pc8: current program counter bits @7~@0: table pointer tblp bits ) ' * * 2 / " in-circuit programming interface
HT48F50E rev. 1.50 11 july 28, 2009 bank 1 of the ram data memory contains only one spe - cial function register, known as the eecr register, which is used for eeprom control and located at ad - dress 40h for all devices. note: most of the ram data memory bits can be di - rectly manipulated using the set [m].i and clr [m].i instructions with the exception of a few dedicated bits. the ram data memory can also be accessed through the memory pointer registers mp0 and mp1. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. special purpose data memory this area of data memory, is located in bank 0, where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . although the special purpose data memory registers are located in bank 0, they will still be accessible even if the bank pointer has selected bank 1. % % 2 2 @ @ 1 @ % 8 1 - 2 4 9 = d ' > ' e 2 2 e . 2 @ + 2 @ - 2 @ bank 0 ram data memory structure / 2 @ " " bank 1 ram data memory structure 2 2 1 1 4 ( 4 ( 4 ( @ & d 6 2 2 1 @ 1 ( 1 4 4 2 2 @ 2 1 @ 2 + @ 2 0 @ 2 / @ 2 . @ 2 - @ 2 , @ 2 $ @ 2 3 @ 2 @ 2 4 @ 2 @ 2 @ 2 " @ 2 @ 1 2 @ 1 1 @ 1 + @ 1 0 @ 1 / @ 1 . @ 1 - @ 1 , @ 1 $ @ 1 3 @ 1 @ 1 4 @ 1 @ 1 @ 1 " @ 1 @ + 2 @ . @ - 2 @ @ = d ' > ' e 2 2 e % 8 1 - 2 4 9 special purpose data memory structure
HT48F50E rev. 1.50 12 july 28, 2009 the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. data .section
data
adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0
code
org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the ram data memory area. these registers ensure correct op - eration of internal functions such as timers, interrupts, watchdog, etc., as well as external functions such as i/o data control. the location of these registers within the ram data memory begins at the address 00h . any unused data memory locations between these special function registers and the point where the general pur - pose memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00h. indirect addressing register iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can ac - cess data from both bank 0 and bank 1. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi - rectly will result in no operation. memory pointer mp0, mp1 for this device, two 8-bit memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to ac - cess data from bank 0 only, while mp1 and iar1 are used to access data from both bank 0 and bank 1.
HT48F50E rev. 1.50 13 july 28, 2009 bank pointer bp the ram data memory is divided into two banks, known as bank 0 and bank 1. with the exception of the eecr register, all of the special purpose registers and general purpose registers are contained in bank 0. bank 1 contains only one register, which is the eeprom control register, known as eecr. selecting the required data memory area is achieved using the bank pointer. if data in bank 0 is to be accessed, then the bp register must be loaded with the value 00, while if data in bank 1 is to be accessed, then the bp register must be loaded with the value 01. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irre - spective of the value of the bank pointer. the eecr register is located at memory location 40h in bank 1 and can only be accessed indirectly using memory pointer mp1 and the indirect addressing register, iar1, after the bp register has first been loaded with the value 01. data can only be read from or written to the eeprom via this register. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within either bank 0 or bank 1. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the pro - gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de- fined location. watchdog timer register wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra - tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi - sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128.
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HT48F50E rev. 1.50 14 july 28, 2009 status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. interrupt control register intc this 8-bit register, known as the intc register, controls the operation of both external and internal timer inter - rupts. by setting various bits within this register using standard bit manipulation instructions, the enable/dis - able function of the external and timer interrupts can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/dis - able and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is en - tered to disable further interrupt and is set by executing the reti instruction. note: in situations where other interrupts may require servicing within present interrupt service rou - tines, the emi bit can be manually set by the program after the present interrupt service rou- tine has been entered. timer/event counter registers this device contains an 8-bit timer/event counter and a 16-bit timter/event counter, which have the associated registers known as tmr0, tmr1h and tmr1l, and are the locations where the timers
s 8-bit and 16-bit values are located. the associated control registers, known as tmr0c and tmr1c, contains the setup information for these two timers. * 5
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HT48F50E rev. 1.50 15 july 28, 2009 input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pc, etc. these la - beled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc, etc., also mapped to specific addresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the con - trol register must be set high, for an output it must be set low. during program initialization, it is important to first setup the control registers to specify which pins are out - puts and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits us - ing the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control reg - isters during normal program operation is a useful fea - ture of these devices. eeprom control register eecr this register is used to control all operations to and from the eeprom data memory. as the eeprom data memory is not mapped like the other memory types, all data to and from the eeprom must be made through this register. the eecr register is located in bank 1 of the data memory, so before use the bank pointer must be setup to a value of 1 . the eecr register can only be read and written to indirectly using the mp1 address pointer. eeprom data memory one of the special features within all these devices is their internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of data memory a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored di - rectly within the product microcontroller. eeprom data memory structure the internal eeprom data memory has a capacity of 256 8 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory. instead it has to be accessed indirectly through the eeprom control register. accessing the eeprom data memory the eeprom data memory is accessed using a set of seven instructions. these instructions control all func - tions of the eeprom such as read, write, erase, enable etc. the internal eeprom structure is similar to that of a standard 3-wire eeprom, for which four pins are used for transfer of instruction, address and data information. these are the chip select pin, cs, serial clock pin, sk, data in pin, di and the data out pin, do. all actions re - lated to the eeprom must be conducted through the eecr register which is located in bank 1 of the ram data memory, in which each of these four eeprom pins is represented by a bit in the eecr register. by ma- nipulating these four bits in the eecr register, in accor- dance with the accompanying timing diagrams, the microcontroller can communicate with the eeprom and carry out the required functions, such as reading and writing data. bit no. label eeprom function 0~3 not implemented bit, read as 0 4 cs eeprom data memory select 5sk serial clock: used to clock data into and out of the eeprom 6di data input: instructions, address and data information are written to the eeprom on this pin 7do data output: data from the eeprom is readout with this bit. will be in a high-impedance con - dition if no data is being read. eecr register - control bit functions * 6 % ' > ' e 2 e , 2 " " " " % " " % " " % f eeprom control register
HT48F50E rev. 1.50 16 july 28, 2009 when reading data from the eeprom, the data will clocked out on the rising edge of sk and appear on do. the do pin will normally be in a high-impedance condi - tion unless a read statement is being executed. when writing to the eeprom the data must be presented first on di and then clocked in on the rising edge of sk. after all the instruction, address and data information has been transmitted, cs should be cleared to 0 to termi - nate the instruction transmission. note that after power on the eeprom must be initialised as described. as indirect addressing is the only way to access the eecr register, all read and write operations to this reg - ister must take place using the indirect addressing reg - ister, iar1, and the memory pointer, mp1. because the eecr control register is located in bank 1 of the ram data memory at location 40h, the mp1 memory pointer must first be set to the value 40h and the bank pointer set to 1. eeprom data memory instruction set control over the internal eeprom, to execute functions such as read, write, disable, enable etc., is implemented through instructions of which there are a total of seven. the related instruction is transmitted to the eeprom via the di bit, after cs has first been set to 1 to enable the eeprom and a start bit 1 has been transmitted. for the read, write and erase instructions, each of the three instructions has its own two bit related instruc - tion code. the 9-bit address should then be transmitted. the address is transmitted in msb first format. for the other four instructions, ewen , ewds , eral and wral , after the start bit has been trans - mitted a 00 instruction code should then follow. the 9-bit address information should then follow. the first two bits of this address is instruction dependant as shown in the table while the remaining bits have don
t care values and can be either high or low. after any write or erase instruction is issued, the internal write function of the eeprom will be used to write the data into the device. as this internal write operation uses the eeprom
s own internal clock, no further instruc - tions will be accepted by the eeprom until the internal write function has ended. after power on and before any instruction is issued the eeprom must be properly in - itialised to ensure proper operation. f @ f ( f @ @ 1 2 * ' * ' clocking data in and out of the eeprom instruction function start bit instruction code address data read read out data byte(s) 1 10 x, a7~a0 d7~d0 erase erase single data byte 1 11 x, a7~a0 write write single data byte 1 01 x, a7~a0 d7~d0 ewen erase/write enable 1 00 11 xxxxx xx ewds erase/write disable 1 00 00 xxxxx xx eral erase all 1 00 10 xxxxx xx wral write all 1 00 01 xxxxx xx d7~d0 instruction set summary
HT48F50E rev. 1.50 17 july 28, 2009 read the read instruction is used to read out one or more bytes of data from the eeprom data memory. to insti - gate a read instruction, the cs bit should be set high, followed by a high start bit and then the instruction code 10 , all transmitted via the di bit. for this device, a dummy bit must be inserted between the last bit of the instruction code and the msb of the address. the ad - dress information should then follow with the msb being transmitted first. after the last address bit, a0, has been transmitted, the data can be clocked out, bit d7 first, on the rising edge of the sk clock signal and can be read via the do bit. however, a dummy 0 bit will first pre - cede the reading of the first data bit, d7. after the full byte has been read out, the internal address will be au - tomatically incremented allowing the next consecutive data byte to be read out without entering further address data. as long as the cs bit remains high, data bit d7 of the next address will automatically follow data bit d0 of the previous address with no dummy 0 being inserted between them. the address will keep incrementing in this way until cs returns to a low value. do will normally be in a high impedance condition until the read in - struction is executed. note that as the read instruc - tion is not affected by the condition of the ewen or ewds instruction, the read command is always valid and independent of these two instructions. write the write instruction is used to write a single byte of data into the eeprom. to instigate a write instruc - tion, the cs bit should be set high, followed by a high start bit and then the instruction code 01 , all transmit - ted via the di bit. for this device, a dummy bit must be inserted between the last bit of the instruction code and the msb of the address. the address information should then follow with the msb bit being transmitted first. after the last address bit, a0, has been transmitted, the data can be immediately transmitted msb first. after all the write instruction code, address and data have been transmitted, the data will be written into the eeprom when the cs bit is cleared to zero. the eeprom does this by executing an internal write-cycle, which will first erase and then write the previously trans - mitted data byte into the eeprom. this process takes place internally using the eeprom
s own internal clock and does not require any action from the sk clock. no further instructions can be accepted by the eeprom until this internal write-cycle has finished. to determine when the write cycle has ended, cs should be again brought high and the do bit polled. if do is low this indi - cates that the internal write-cycle is still in progress, however, the do bit will change to a high value when the internal write-cycle has ended. before a write in- struction is transmitted an ewen instruction must have been transmitted at some point earlier to ensure that the erase/write function of the eeprom is enabled. f 2 1 2 , 2 2 , , # ' ' ' # % 7 1 read timing f 1 2 ' * * c 4 , 1 2 2 , 1 write timing
HT48F50E rev. 1.50 18 july 28, 2009 ewen/ewds the ewen instruction is the erase/write enable in - struction and the ewds instruction is the erase/write disable instruction. to instigate an ewen or ewds instruction, the cs bit should first be set high, followed by a high start bit and then the instruction code 00 . for the ewen instruction, a 11 should then be transmit - ted and for the ewds instruction a 00 should be transmitted. following on from this, 7-bits of don
t care data should then be transmitted to complete the instruc - tion. if the device is already in the erase write disable mode then no write or erase operations can be executed thus protecting the internal eeprom data. before any write or erase instruction is executed an ewen in - struction must be issued. after the ewen instruction is executed, the device will remain in the erase write enable mode until a subsequent ewds instruction is issued or until the device is powered down. eral the eral instruction is used to erase the whole con - tents of the eeprom memory. after it has been exe - cuted all the data in the eeprom will be set to 1 .to instigate this instruction, the cs bit should be set high, followed by a high start bit and then the instruction code 00 . following on from this, a 10 should then be transmitted. this should be followed by 7-bits of don
t care data to complete the instruction. after the eral instruction code has been transmitted, the eeprom data will be erased when the cs bit is cleared to zero. the eeprom does this by executing an internal write-cycle. this process takes place internally using the eeprom
s own internal clock and does not require any action from the sk clock. no further instructions can be accepted by the eeprom until this internal write-cycle has finished. to determine when the write cycle has ended, cs should be again brought high and the do bit polled. if d0 is low this indicates that the inter - nal write-cycle is still in progress, however the d0 bit will change to a high value when the internal write-cycle has ended. before an eral instruction is transmitted an ewen instruction must have been transmitted at some point earlier to ensure that the erase/write function of the eeprom is enabled. wral the wral instruction is used to write the same data into the entire eeprom. to instigate this instruction, the cs bit should be set high, followed by a high start bit and then the instruction code 00 . following on from this, a 01 should then be transmitted. this should be fol - lowed by 7-bits of don
t care data. the data informa - tion should then follow with the msb bit being transmitted first. after the instruction code and data have been transmitted, the data will be written into the eeprom when the cs bit is cleared to zero. the eeprom does this by executing an internal write-cycle. this process takes place internally using the eeprom
s own internal clock and does not require any action from the sk clock. no further instructions can be accepted by the eeprom until this internal write-cycle has finished. to determine when the write cycle has ended, cs should be again brought high and the do bit polled. if d0 is low this indicates that the internal write-cycle is still in progress, however the d0 bit will change to a high value when the internal write-cycle has ended. before a wral instruction is transmitted an ewen instruction must have been transmitted at some point earlier to ensure that the erase/write function of the eeprom is enabled. the wral instruction will automatically erase any previously written data making it unnecessary to first issue an erase instruction. f ' 2 1 2 " & " 6 g 1 1 h h h h h h h ! ! , ! ' i " & g 2 2 ewen/ewds timing f ' * 4 * c 1 222 1 h h h h h h h ! ! , ! ' i eral timing
HT48F50E rev. 1.50 19 july 28, 2009 erase the erase instruction is used to erase data at a specified address. the data at the address specified will be set to 1 . to instigate an erase instruction, the cs bit should be set high, followed by a high start bit and then the instruction code 11 , all transmitted via the di bit. for this device, a dummy bit must be inserted be - tween the last bit of the instruction code and the msb of the address. the address information should then follow with the msb bit being transmitted first. after all the erase instruction code and address have been transmitted, the data at the specified address will be erased when the cs bit is cleared to zero. the eeprom does this by executing an internal write cycle which will set all data at the specified address to 1. this process takes place internally using the eeprom
s own internal clock and does not require any action from the sk clock. no further instructions can be accepted by the eeprom until the write cycle has fin- ished. to determine when the write cycle has ended, the cs should be again brought high and the do bit polled. if the do bit is low this indicates that the write-cycle is still in progress, however, the do bit will change to a high value when the write-cycle has ended. before an erase instruction is transmitted, an ewen instruc - tion must have been transmitted at some point earlier to ensure that the erase/write function of the eeprom is enabled. internal write cycle the write or erase instructions, write , erase , eral or wral will all use the eeprom
s internal write cycle function. as this function is completely inter - nally timed, the sk clock is not required. as the mcu has no control over the timing of this write cycle, it must still have some way of knowing when the internal write cycle has completed. this is because, when the internal write cycle is executing, the eeprom will not accept any fur - ther instructions from the mcu. the mcu must therefore wait until the write cycle has finished before sending any further instructions. one way for the mcu to know when the write cycle has terminated is to poll the do bit after the cs bit has is- sued a low pulse. the low going edge of this cs bit pulse will initiate the internal write cycle, when the bit is returned high the do bit will go low to indicated that the write cycle is in progress. when the do bit returns high this indicates that the internal write cycle has ended and that the eeprom is ready to receive further instruc- tions. f ' 1 * 4 * c 2 , 2 22 1 h h h h h h h ! ! , ! ' i wral timing f 1 1 ' * 4 * c , 1 2 - . 1 erase timing
HT48F50E rev. 1.50 20 july 28, 2009 initialising the eeprom after the mcu is powered on and if the eeprom is to be used, it must be initialised in a specific way before any user instructions are transmitted. this is achieved by first transmitting an ewen instruction, then by issu - ing a write instruction to write random data to any sin - gle address in the eeprom. the initialisation procedure can then be terminated by issuing an ewds instruction, however at this point, if actual user data is to be imminently written to the eeprom, this last step is optional. 6 < ' ' > ) ' ) c # ' g e 1 e )
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* ' ' internal write cycle busy polling the following is an example program of how this can be implemented: mov a,01h mov bp,a ; set to bank 1 mov a,40h mov mp1,a ; set mp1 to eecr address call ewen ; subroutine to run ewen instructions mov a, 7fh mov eeaddr, a mov a, 55h mov eedata, a call write ; subroutine to run write instruction ; write 55h data to address 7fh call ewds ; optional subroutine to run ewds instruction eeprom program examples the following short programs gives examples of how to send instructions, read and write to the eeprom. these pro - grams can form a basis of understanding as to how the internal eeprom memory is to be used to store and retrieve data. example 1 definitions and sending instructions to the eeprom _cs equ iar1.4 ; eeprom lines setup to have a corresponding _sk equ iar1.5 ; bit in the indirect addressing register iar1 _di equ iar1.6 ; eeprom can only be indirectly addressed using ; mp1 _do equ iar1.7 _eecr equ 40h ; setup address of the eeprom control register c_addr_length equ 8 ; address length 8-bits c_data_length equ 8 ; data length always 8-bits ; data .section at 70h
data
ee_command db ? ; stores the read or write instruction ; information addr db ? ; store write data or read data address wr_data db ? ; store read or write data count db ? ; temporary counter ;
HT48F50E rev. 1.50 21 july 28, 2009 writecommand: ; write instruction code subroutine mov a,3 ; read, write and erase instructions are 3 bits ; long mov count,a set _sk ; dummy bit transmission for 256x8 bit eeprom memory ; capacity clr _sk ; not required for 128x8 bit eeprom memory capacity devices writecommand_0: clr _di ; prepare the transmitted bit sz ee_command.7 ; check value of highest instruction code bit set _di set _sk clr _sk clr c rlc ee_command ; get next bit of instruction code sdz count ; check if last bit has been transmitted jmp writecommand_0 clr _di ret example 2 transmitting an address to the eeprom writeaddr: ; write address subroutine mov a,c_addr_length ; setup address length mov count,a set _sk ; dummy bit transmission for 256 8 bit eeprom memory ; capacity clr _sk ; not required for 128x8 bit eeprom memory capacity devices writeaddr_0: clr _di sz addr.7 ; check value of address msb set _di clr c rlc addr ; get next address bit set _sk clr _sk sdz count ; check if address lsb has been written jmp writeaddr_0 clr _di ret example 3 writing data to the eeprom writedata: mov a,c_data_length ; setup data length mov count,a writedata_0: clr _di sz wr_data.7 ; check value of data msb set _di clr c rlc wr_data ; get next address bit set _sk clr _sk sdz count ; check if data lsb has been written jmp writedata_0 clr _cs ; cs low edge initiates internal write cycle set _cs ; cs high edge allows do to be used to indicate ; end of write cycle snz _do ; poll for do high to indicate end of write ; cycle jmp $-1 ret
HT48F50E rev. 1.50 22 july 28, 2009 example 4 reading data from the eeprom readdata: mov a,c_data_length ; setup data length mov count,a clr wr_data readdata_0: clr c rlc wr_data set _sk sz _do ; check value of data msb set wr_data.0 clr _sk sdz count ; check if lsb has been received jmp readdata_0 mov a,wr_data ret input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. this device provides 33 bidirectional input/output lines labeled with port names pa, pb, pc, pd and pg. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains un- changed until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via configuration options and are implemented using a weak pmos transistor. note that if the pull-high option is selected, then all i/o pins on that port will be con - nected to pull-high resistors, individual pins cannot be selected for pull-high resistor options. port a wake-up each device has a halt instruction enabling the microcontroller to enter a power down mode and pre - serve power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. after a halt instruction forces the microcontroller into entering a halt condition, the pro - cessor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via exter - nal switches. note that each pin on port a can be se- lected individually to have this wake-up feature. i/o port control registers each i/o port has its own control register pac, pbc, pcc, pdc and pgc, to control the input/output configu- ration. with this control register, each cmos output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its asso - ciated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos out - put. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. note that there is an addi - tional configuration option for port a that can select whether the inputs on this port are schmitt trigger types or non-schmitt trigger types. inputs for the other ports are all schmitt trigger type.
HT48F50E rev. 1.50 23 july 28, 2009 pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control. buzzer the buzzer pins bz and bz are pin-shared with i/o pins pb0 and pb1. the buzzer function is selected via a configuration option and remains fixed after the de - vice is programmed. note that the corresponding bits of the port control register, pbc, must setup the pins as outputs to enable the buzzer outputs. if the pbc port control register has setup the pins as inputs, then the pins will function as normal logic inputs with the usual pull-high options, even if the buzzer configura - tion option has been selected. external interrupt input the external interrupt pin int is pin-shared with the i/o pin pg0. for the shared function pin to operate as an external interrupt pin and not as a normal i/o pin, the corresponding external interrupt enable bits in the intc interrupt control register must be correctly set. for applications not requiring an external interrupt in- put, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the external in- terrupt enable bits in the intc register must be dis- abled. external timer/event counter input this device contains an 8-bit timer/event counter 0 which has an external pin known as tmr0 and a 16-bit timer/event counter 1 which has an external pin known as tmr1. these two external timer pins are individual input pins in 48-pin package but are pin-shared with i/o pin pc0 or pc5 in 28-pin package by internal wire bond. if these shared pins are to be used as timer/event counter inputs, then the timer/event counters must be configured to be in the event counter or pulse width measurement mode. this is achieved by setting the appropriate bits in the relevant timer/event counter control registers. these pins must also be setup as inputs by setting the appropriate bits in the port control register. pull-high resistor option can also be selected via the appropri - ate port pull-high configuration option. if these shared pins are to be used as normal i/o pins, then the exter - nal timer input functions must be disabled, by ensur - ing that the corresponding timer/event counters are configured to be in the off mode or timer mode. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional under - standing of the i/o pins. note also that the specified pins refer to the largest device package, therefore not all pins specified will exist on all devices. & ! % % & ! % '
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6 8 2 9 2 8 2 9 1 8 . 9 pb, pc, pd and pg input/output ports programming considerations within the user program, one of the first things to con - sider is port initialization. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, pac, pbc, pcc, pdc and pgc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa, pb, pc, pd and pg, are first programmed. selecting which pins are in - puts and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the en - tire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. 1 + 0 / 1 + 0 / & ' c read/write timing
HT48F50E rev. 1.50 25 july 28, 2009 timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. this device contains two count-up timers of 8-bit and 16-bit capacities respectively. as each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. the provision of an internal prescaler for the 8-bit timer/event counter to the clock circuitry gives added range to the timer. there are two types of registers related to the timer/event counters. the first is the register that con - tains the actual value of the timer/event counter and into which an initial value can be preloaded, and is known as tmr0, tmr1h or tmr1l. reading from this register retrieves the contents of the timer/event coun - ter. the second type of associated register is the timer control register, which defines the timer options and determines how the timer/event counter is to be used, and has the name tmr0c or tmr1c. this device can have the timer clocks configured to come from the inter - nal clock sources. in addition, the timer clock source can also be configured to come from the external timer pins. the external clock source is used when the timer/event counter is in the event counting mode, the clock source being provided on the external timer pin. the pin has the name tmr0 or tmr1 and is pin-shared with an i/o pin. depending upon the condition of the t0e or t1e bit in the timer control register, each high to low, or low to high transition on the external timer input pin will incre - ment the timer/event counter by one. configuring the timer/event counter input clock source the timer/event counter
s clock can originate from var - ious sources. the system clock source is used when the timer/event counter 0 is in the timer mode or in the pulse width measurement mode. the system clock is di - vided by a prescaler, the division ratio of which is condi - tioned by the timer control register named tmr0c bits t0psc2~t0psc0. the instruction clock source (sys - tem clock source divided by 4) is used when the timer/event counter 1 is in the timer mode or in the pulse width measurement mode. the external clock source is used when the timer/event counter is in the event counting mode, the clock source being provided on the external timer pin, tmr0 or tmr1. depending upon the condition of the t0e or t1e bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. 2 2 " " b ' 2 6 '
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HT48F50E rev. 1.50 26 july 28, 2009 timer registers tmr0, tmr1l/tmr1h the timer registers are special function registers located in the special purpose ram data memory and are the places where the actual timer values are stored. for 8-bit timer/event counter 0, this register is known as tmr0. for 16-bit timer/event counter 1, the timer reg - isters are known as tmr1l and tmr1h. the value in the timer registers increases by one each time an inter - nal clock pulse is received or an external transition oc - curs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer or ffffh for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and con - tinue counting. to achieve a maximum full range count of ffh for the 8-bit timer or ffffh for the 16-bit timer, the preload reg - isters must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. however, if the timer/event counter is enabled and counting, any new data written into the preload data registers during this period will re- main in the preload registers and will only be written into the timer registers the next time an overflow occurs. for the 16-bit timer/event counter which has both low byte and high byte timer registers, accessing these reg- isters is carried out in a specific way. it must be note when using instructions to preload data into the low byte timer register, namely tmr1l, the data will only be placed in a low byte buffer and not directly into the low byte timer register. the actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely tmr1h, is executed. on the other hand, using instruc - tions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. at the same time the data in the low byte buffer will be transferred into its associated low byte timer register. for this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. it must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associ - ated low byte buffer. after this has been done, the low byte timer register can be read in the normal way. note that reading the low byte timer register will result in read - ing the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control register tmr0c, tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their control register, which has the name tmr0c or tmr1c. it is the timer control regis - ter together with its corresponding timer register that control the full operation of the timer/event counter. before the timer/event counter can be used, it is es - sential that the timer control register is fully pro - grammed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer/event counter is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair t0m1/t0m0 or t1m1/t1m0, must be set to the required logic levels. the timer/event counter on/off bit, which is bit 4 of the timer control register and known as t0on or t1on, provides the ba- sic on/off control of the timer/event counter. setting the bit high allows the timer/event counter to run, clearing the bit stops it running. for 8-bit timer/event counter 0 with prescaler, bits 0~2 of the timer control register de - termine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer/event counter is in the event count or pulse width measurement mode, the ac - tive transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as t0e or t1e.
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HT48F50E rev. 1.50 28 july 28, 2009 configuring the timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal inter - rupt signal each time the timer/event counter over - flows. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock, f sys is used as the inter - nal clock for 8-bit timer/event counter 0 and f sys /4 is used as the internal clock for 16-bit timer/event coun - ter 1. however, the clock source, f sys , for 8-bit timer is further divided by a prescaler, the value of which is de - termined by the prescaler rate select bits t0psc2~t0psc0, which are bits 2~0 in the timer con - trol register. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. each time an internal clock cycle occurs, the timer/event counter increments by one. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc, is reset to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be re- corded by the timer/event counter. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode, the external timer pin, tmr0 or tmr1, is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit t0e or t1e, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the counter will incre - ment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex - ternal timer pin. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width measure - ment mode bit7 bit6 11 % ; 1 ; + ; 6 ; 6 ; 1 timer mode timing diagram ; + " : % 2 " 1 " g 1 ; 0 ; 1 event counter mode timing diagram
HT48F50E rev. 1.50 29 july 28, 2009 in this mode the internal clock, f sys is used as the inter - nal clock for 8-bit timer/event counter 0 and f sys /4 is used as the internal clock for 16-bit timer/event coun - ter 1. however, the clock source, f sys , for 8-bit timer is further divided by a prescaler, the value of which is de - termined by the prescaler rate select bits t0psc2~t0psc0, which are bits 2~0 in the timer con - trol register. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is re - ceived on the external timer pin. if the active edge select bit t0e or t1e, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, tmr0 or tmr1, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automati - cally reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin re - turns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the exter - nal timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event coun - ter in the pulse width measurement mode, the second is to ensure that the port control register configures the pin as an input. programmable frequency divider (pfd) and buzzer application operating similar to a programmable frequency divider, the buzzer function within the microcontroller provides a means of producing a variable frequency output suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency generator. the bz and bz are a complimentary pair and pin-shared with i/o pins, pb0 and pb1. the function is selected via configuration option, however, if not selected, the pins can operate as normal i/o pins. note that the bz pin is the inverse of the bz pin generating a kind of differential output and supplying more power to connected inter- faces such as buzzers. the clock source for the buzzer circuit can come from the timer 0 or timer 1 overflow signal selected via the configuration option. the output frequency is controlled by loading the required values into the timer prescaler and timer registers to give the required division ratio. the counter will begin to count-up from this preload reg - ister value until full, at which point an overflow signal is generated, causing both the bz and bz outputs to change state. the counter will then be automatically re - loaded with the preload register value and continue counting-up. if the configuration option has selected the buzzer func - tion, then for both buzzer outputs to operate, it is essen - ; 1 ; + ; 0 ; / " : % 2 6 1 6 8 ) # 2 " 1 " g 2 9 % % % ' b c
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c 1 7 pulse width measure mode timing diagram
HT48F50E rev. 1.50 30 july 28, 2009 tial that the port b control register pbc bit 0 and pbc bit 1 are setup as outputs. if only one pin is setup as an out - put, the other pin can still be used as a normal data input pin. however, if both pins are setup as inputs then the buzzer will not function. the buzzer outputs will only be activated if bit pb0 is set to 1 . this output data bit is used as the on/off control bit for the buzzer outputs. note that the bz and bz outputs will both be low if the pb0 output data bit is cleared to 0 . the condition of data bit pb1 has no effect on the overall control of the bz and bz pins. using this method of frequency generation, and if a crystal oscillator is used for the system clock, very pre- cise values of frequency can be generated. prescaler the 8-bit timer in the device possesses a prescaler. bits 2~0 of the timer control register tmr0c, named t0psc2~t0psc0,define the prescaling stages of the internal clock source of the 8-bit timer/event counter. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quires the use of an external pin for correct operation. as the external timer pin is pin-shared with an i/o pin, it must be configured correctly to ensure it is setup for use as a timer/event counter input and not as a normal i/o pin. this is implemented by ensuring that the mode se - lect bits in the timer/event counter control register, se - lect either the event counter or pulse width measurement mode. in 28-pin package, the associated port control register bits for the external timer input pins must be set high to ensure that these pins are setup as an inputs. any pull high configuration for these pins will remain valid even if these pins are used as timer/event counter inputs. in 48-pin package, the ex - ternal timer input pins are independent pins without pull-high resistors and not pin-shared with i/o pins. there are not any port control register bits that will af - fect the timer/event counters function. programming considerations when configured to run in the timer mode, the internal system clock and instruction clock (system clock divided by 4) are used as the internal timer clock sources for 8-bit and 16-bit timers resepctively and are therefore synchronized with the overall operation of the microcontroller. in this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width measurement mode, the internal system clock or in- struction clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an ex- ternal event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a re- sult there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is config - ured to be in the event counting mode which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read or if data is writ - ten to the preload registers, the clock is inhibited to avoid errors, however as this may result in a counting er - ror, this should be taken into account by the program - mer. care must be taken to ensure that the timers are properly initialised before using them for the first time. the associated timer interrupt enable bits in the inter - rupt control register must be properly set otherwise the internal interrupt associated with the timer will remain in - active. the edge select, timer mode and clock source control bits in timer control register must also be cor - rectly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer register before the timer is switched on; this is because after power-on the initial value of the timer register is un - known. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the b c ) 4 l l 4 2 4 5 % 4 2 4 5 % 4 1 pfd output control
HT48F50E rev. 1.50 31 july 28, 2009 timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed af - ter the timer mode bits have been properly setup. set - ting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if ex - ecuted as a single timer control register byte write in - struction. when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irre - spective of whether the timer interrupt is enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condi - tion. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter - nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the inter - rupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter tobe in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector reti org 08h ; timer/event counter 0 interrupt vector jmp tmr0int ; jump here when timer/event counter 0 overflows org 0ch ; timer/event counter 1 interrupt vector jmp tmr1int ; jump here when timer/event counter 1 overflows : org 20h ; main program : ;internal timer/event counter 0 interrupt routine tmr0int: : ; timer/event counter 0 main program placed here : reti : ;internal timer/event counter 1 interrupt routine tmr1int: : ; timer/event counter 1 main program placed here : reti : begin: ;setup timer/event counter 0 registers mov a,09bh ; setup preload value for timer/event counter 0 timer counts from ; this value to ffh mov tmr0,a ; mov a,081h ; setup timer control register tmr0c mov tmr0c,a ; timer mode and prescaler set to /4 ;setup timer/event counter 1 registers mov a,09bh ; setup low byte preload value for timer/event counter 1 mov tmr1l,a ; low byte must be setup before high byte mov a,0e8h ; setup high byte preload value for timer/event counter 1 mov tmr1h,a ; mov a,080h ; setup timer control register tmr1c mov tmr1c,a ; timer/event counter 1 has no prescaler and clock source is f sys /4 ; setup interrupt register mov a,00dh ; enable master interrupt and timer interrupts mov intc,a : set tmr0c.4 ; start timer/event counter 0 note mode bits must be previously setup set tmr1c.4 ; start timer/event counter 1 note mode bits must be previously setup
HT48F50E rev. 1.50 32 july 28, 2009 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains a single external interrupt and two internal timer interrupt functions. the external interrupt is controlled by the action of the external int pin, while the internal interrupts are controlled by the timer/event counters overflow. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by a single intc register, which is located in the ram data memory. by controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding re - quest flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a timer/event counter overflow or the external interrupt line being pulled low will all generate an interrupt re- quest by setting their corresponding request flag, if their appropriate interrupt enable bit is set. when this hap- pens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corre - sponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will take program execution to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate inter - rupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original pro - gram counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the following dia - gram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou- tine, to allow interrupt nesting. if the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. , *
! % " 1 =
2 =
' 6 % ' > ' e 2 e , 2 " 2 " " " " b 2 % " 1 = 2 = ' " b 2 %
1 = b 2 = b " 2 " : % " 1 = 2 = ' " : %
1 = b 2 = b 1 " 1 " b 1 %
1 = b 2 = b " b 1 % " 1 = 2 = ' interrupt control register
HT48F50E rev. 1.50 33 july 28, 2009 ' ' c ) " : %
" " b 2 %
2 " " " 2 " %
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# ( ) ' " ' " b 1 %
1 " 1 interrupt structure interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority external interrupt 1 timer/event counter 0 overflow 2 timer/event counter 1 overflow 3 in cases where both external and internal interrupts are enabled and where an external and internal interrupt oc- curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the intc reg- ister can prevent simultaneous occurrences. external interrupt for an external interrupt to occur, the global interrupt en - able bit, emi, and external interrupt enable bit, eei, must first be set. an actual external interrupt will take place when the external interrupt request flag, eif, is set, a situ - ation that will occur when a high to low transition appears on the int line. the external interrupt pin is pin-shared with an i/o pin pg.0 and can only be configured as an ex - ternal interrupt pin if the corresponding external interrupt enable bit in the intc register has been set. the pin must also be setup as an input by setting the corresponding pgc.0 bit in the port control register. when the interrupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external inter - rupt request flag, eif, will be automatically reset and the emi bit will be automatically cleared to disable other inter - rupts. note that any pull-high resistor configuration op - tions on this pin will remain valid even if the pin is used as an external interrupt input. timer/event counter interrupts for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, et0i or et1i, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, t0f or t1f, is set, a situation that will occur when the timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow oc - curs, a subroutine call to the timer interrupt vector at lo - cation 08h or 0ch, will take place. when the interrupt is serviced, the timer interrupt request flag, t0f or t1f, will be automatically reset and the emi bit will be automati- cally cleared to disable other interrupts. programming considerations by disabling the interrupt enable bits, a requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc register until the corresponding in- terrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the con - tents of the register or status register are altered by the interrupt service program, which may corrupt the de - sired control sequence, then the contents should be saved in advance.
HT48F50E rev. 1.50 34 july 28, 2009 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. " * ! 2 7 3 * power-on reset timing chart " 2 7 1 1 2 2 * * 2 7 2 1 1 2 enhanced reset circuit " ! 2 7 3 * 2 7 / * res reset timing chart " * * 2 7 1 1 2 2 basic reset circuit
HT48F50E rev. 1.50 35 july 28, 2009 low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the bat - tery, the lvr will automatically reset the device inter - nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1. watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal regis - ters of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. ( * ! low voltage reset timing chart & ! ! wdt time-out reset during normal operation timing chart & ! ! wdt time-out reset during power down timing chart
HT48F50E rev. 1.50 36 july 28, 2009 HT48F50E register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xx xxxx uu uuuu uu uuuu uu uuuu wdts 0000 0111 0000 0111 0000 0111 uuuu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc 00 000 00 000 00 000 uu uuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 01 00 01 00 01 uu uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pg 1 1 1 u pgc 1 1 1 u note: u stands for unchanged x stands for unknown stands for unimplemented
HT48F50E rev. 1.50 37 july 28, 2009 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. two types of system clocks can be selected while various clock source options for the watchdog timer are provided for maximum flexibility. all oscillator options are selected through the configuration options. the two methods of generating the system clock are: external crystal/resonator oscillator external rc oscillator one of these two methods must be selected using the configuration options. more information regarding the oscillator is located in application note ha0075e on the holtek website. external crystal/resonator oscillator the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feed - back for oscillation, and will normally not require exter - nal capacitors. however, for some crystals and most resonator types, to ensure oscillation and accurate fre - quency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer
s specifica - tion. the external parallel feedback resistor, rp, is nor - mally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, rf typical values @ 5v, 25 c ca cb rf 8pf 10pf 800k oscillator internal component values crystal oscillator c1 and c2 values crystal frequency c1 c2 cl 12mhz tbd tbd tbd 8mhz tbd tbd tbd 4mhz tbd tbd tbd 1mhz tbd tbd tbd note: 1. c1 and c2 values are for guidance only. 2. cl is the crystal manufacturer specified load capacitor value. crystal recommended capacitor values resonator c1 and c2 values resonator frequency c1 c2 3.58mhz tbd tbd 1mhz tbd tbd 455khz tbd tbd note: c1 and c2 values are for guidance only. resonator recommended capacitor values external rc oscillator using the external system rc oscillator requires that a resistor, with a value between 24k and 1m , is con- nected between osc1 and vdd, and a capacitor is con- nected to ground. the generated system clock divided by 4 will be provided on osc2 as an output which can be used for external synchronization purposes. note that as the osc2 output is an nmos open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. although this is a cost ef - fective oscillator configuration, the oscillation frequency can vary with vdd, temperature and process variations and is therefore not suitable for applications where tim - ing is critical or where accurate oscillator frequencies are required. for the value of the external resistor r osc refer to the holtek website for typical rc oscillator vs. temperature and vdd characteristics graphics. note that it is the only microcontroller internal circuitry to - gether with the external resistor, that determine the fre - quency of the oscillator. the external capacitor shown on the diagram does not influence the frequency of os - cillation. 1 + c ' ! $ ' ' * $ - 1 + % 6 = 1 7 % ' 7 + 7 #
# # ) 1 + % # b % % c ' , % 7 crystal/resonator oscillator 1 / , 2 % * + c < / 6 % external rc oscillator
HT48F50E rev. 1.50 38 july 28, 2009 watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 sat5v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the halt mode or sleep mode. when the device enters this mode, the nor - mal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consump - tion to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requir - ing a full reset. this feature is extremely important in ap - plication areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc- tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi - nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. care must also be taken with the loads, which are connected to i/os, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam- ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup via an individual config - uration option to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up oc - curs, the program will resume execution at the instruc - tion following the halt instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled.
HT48F50E rev. 1.50 39 july 28, 2009 no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by one of two sources selected by con - figuration option: its own self-contained dedicated inter - nal wdt oscillator, or the instruction clock which is the system clock divided by 4. note that if the wdt configu - ration option has been disabled, then any instruction re - lating to its operation will result in no operation. the internal wdt oscillator has an approximate period of 65 s at a supply voltage of 5v. if selected, it is first di - vided by 256 via an 8-stage counter to give a nominal period of 17ms. note that this period can vary with vdd, temperature and process variations. for longer wdt time-out periods the wdt prescaler can be utilized. by writing the required value to bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2, longer time-out periods can be achieved. with ws0, ws1 and ws2 all equal to 1, the division ratio is 1:128 which gives a maxi- mum time-out period of about 2.1s. a configuration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator. if the in - struction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the sys - tem cannot be restarted by the wdt and can only be re - started using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how - ever, if the system is in the power down mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, succes- sive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly, after the clr wdt2 instruc- tion has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. & + .
! , 2 & % & + 2 2 2 2 1 1 1 1 & 1 2 2 1 1 2 2 1 1 & 2 2 1 2 1 2 1 2 1 & 1 = 1 1 = + 1 = / 1 = $ 1 = 1 - 1 = 0 + 1 = - / 1 = 1 + $ 6 ' & 1 & 2 watchdog timer register
application circuits HT48F50E rev. 1.50 40 july 28, 2009 configuration options configuration options refer to certain options within the mcu that are programmed into the flash type program mem - ory device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware program - ming tools, once they are selected they cannot be changed later by the application software. all options must be defined for proper system function, the details of which are shown in the table. no. options 1 watchdog timer: enable or disable 2 watchdog timer clock source: wdt oscillator or f sys /4 3 clrwdt instructions: 1 or 2 instructions 4 pa0~pa7: wake-up enable or disable (bit option) 5 pa, pb, pc, pd and pg: pull-high enable or disable (by port) 6 pa input type: cmos or schmitt trigger 7 buzzer function: enable or normal i/o 8 buzzer clock source: timer 0 or timer 1 9 system oscillator: crystal or rc 10 lvr function: enable or disable 2 j , 4 + j 4 , 2 j , 4 2 4 5 4 1 4 5 2 1 2 6 " 1 + 2 7 1 1 2 2 * * 2 7 1 * ! * $ - 2 j ,
! $ ' ' $ $ ! 8 + . - 9 , ! $ ! ! 1 d h & ! & 2 j & + & & % c
% ( & 1
( & +
1 + ( ( c < / & & c
% watchdog timer
HT48F50E rev. 1.50 41 july 28, 2009 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT48F50E rev. 1.50 42 july 28, 2009 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT48F50E rev. 1.50 43 july 28, 2009 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT48F50E rev. 1.50 44 july 28, 2009
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT48F50E rev. 1.50 45 july 28, 2009
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1
s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1
s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT48F50E rev. 1.50 46 july 28, 2009
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT48F50E rev. 1.50 47 july 28, 2009
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT48F50E rev. 1.50 48 july 28, 2009
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT48F50E rev. 1.50 49 july 28, 2009
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT48F50E rev. 1.50 50 july 28, 2009
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT48F50E rev. 1.50 51 july 28, 2009
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT48F50E rev. 1.50 52 july 28, 2009
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT48F50E rev. 1.50 53 july 28, 2009
package information 28-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1375 1395 b 278 298 c 125 135 d 125 145 e1 6 20 f5 0 70 g 100 h 295 315 i 375 HT48F50E rev. 1.50 54 july 28, 2009 + $ 1 1 . 1 / 4 " @
28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c
697 713 d 104 e 50 f4 12 g16 50 h8 13 08 HT48F50E rev. 1.50 55 july 28, 2009 + $ 1 1 . 1 / 4 i @ "
28-pin ssop (150mil) outline dimensions symbol dimensions in mil min. nom. max. a 228 244 b 150 157 c8 12 c
386 394 d54 60 e 25 f4 10 g22 28 h7 10 08 HT48F50E rev. 1.50 56 july 28, 2009 + $ 1 1 . 1 / 4 i @ "
48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c
613 637 d85 99 e 25 f4 10 g25 35 h4 12 08 HT48F50E rev. 1.50 57 july 28, 2009 / $ 1 + . + / 4 i @ "
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 HT48F50E rev. 1.50 58 july 28, 2009 4 1 +
ssop 48w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.00.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 32.2 +0.3/-0.2 t2 reel thickness 38.20.2 HT48F50E rev. 1.50 59 july 28, 2009
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 HT48F50E rev. 1.50 60 july 28, 2009 1 & 1 2 " f 2 4 2 2 %
% 1 ' # # ' # ' 7 @
ssop 48w symbol description dimensions in mm w carrier tape width 32.00.3 p cavity pitch 16.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 14.20.1 d perforation diameter 2 min. d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 12.00.1 b0 cavity width 16.20.1 k1 cavity depth 2.40.1 k2 cavity depth 3.20.1 t carrier tape thickness 0.350.05 c cover tape width 25.50.1 HT48F50E rev. 1.50 61 july 28, 2009 1 1 2 " f + 4 2 2 & f 1 %
% 1 ' # # ' # ' 7 @ 8 9 @ 8 " % 9
HT48F50E rev. 1.50 62 july 28, 2009 copyright 2009 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek
s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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